Appeal No. 1998-0931 Page 12
Application No. 08/139,619
playboard and communication devices (col. 6, lines 34-36).
Figure 7 discloses a schematic of the playboard controller
(col. 2, lines 41 and 42). Figure 3A discloses an
implementation of the playboard 40 which includes CRT display
60 which is connected, via buses 62-64 to CRT controller 61.
Controller 61 generates a composite video signal necessary for
display of a game (col. 3, line 61 through col. 4, line 1)
e.g., Keno (figure 6). Hedges further discloses (col. 4,
lines 14-28) that:
In FIG. 7, controller 61 generates the display
under control of a sequence of control bytes of data
which are stored in a display storage memory 92.
Both the processor 41 and controller 61 have the
ability to access the display storage memory 92 via
data bus 96. Processor 41 stores the appropriate
control bytes into the display storage memory via
address bus 95,97 and decode logic 93, as determined
by the game selected and the subsequent play of the
game. Controller 61 of FIG. 3A reads the stored
data from display storage memory 92 of FIG. 7 once
every 1/30th of a second and generates the
appropriate TV signals on buses 62-64, 67 to cause
the display of the particular game selected on
monitor 60 by the processor determined information.
From these teachings of Hedges, we find that the
circuitry of processor 41 is for processing data relating to
the playboard display and not the TV 21 or live game display
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