Appeal No. 1998-2749
Application 08/637,062
inherent in Hausman. The DMA ring buffer is contained in the host
memory, which is a different memory from the RX FIFO 170 which the
Examiner relies on as the claimed "buffer memory" in claim 12.
Thus, indices for writing and reading into the DMA Ring Buffer are
not relevant to claims 13 and 14. However, the RX RAM FIFO 170 is
a random access memory (RAM) first-in first-out (FIFO) buffer. It
was notoriously well known to those of ordinary skill in the
computer art that RAM FIFOs have means to generate storage
addresses for writing and reading data in a first-in first-out
order; i.e., new data is written to the logical bottom of the
buffer and the oldest data is read from the logical top of the
buffer with indices (pointers) to keep track of the addresses of
the top and bottom data values (like the DMA ring buffer Write
index and Read index). Hausman discloses (col. 8, lines 19-23):
"If DMA mode is initiated, the DMA controller will begin copying
bytes from the top of RX FIFO 170 into the DMA ring buffer, while
receive circuitry 130 may be continuing to add data to the bottom
of RX FIFO 170." Manifestly, Hausman inherently must have means
for determining the addresses of the top and bottom of the FIFO
buffer for reading and writing, respectively. For these reasons,
we sustain the rejection of claims 13 and 14.
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