Appeal No. 1998-3078 Page 2
Application No. 08/365,617
transistor. Besides the transistor and capacitor, the
substrate level includes a "strap" connecting a given
transistor to a given capacitor and the required isolation
between cells. The interconnect level includes wordlines that
interconnect the gate electrodes of transistors in DRAM cells
and sufficient space between the wordlines to prevent shorting
therebetween. As such, the total area taken up by a given
DRAM cell is determined by the larger of the area of all the
structures on the silicon substrate level and the area of the
connectors and spaces therebetween on the connector level.
Whichever of these two is larger determines the area of the
cell.
The appellant's invention uses segment gates and spacer
wordlines to save area on the connector level of a DRAM cell.
Because the total area of each cell could not be
correspondingly reduced unless the area of each cell at the
silicon substrate level was similarly reduced, the invention
provides a cell design on the silicon level in which a
transistor is adjacent a trench capacitor and formed in
conventional seam-free single crystal silicon using a smaller
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