Appeal No. 1998-3078 Page 3
Application No. 08/365,617
area on the silicon level than the conventional cell. The
invention further provides a segment gate
and spacer word line integrated with this smaller silicon
level cell design to reduce the area of the whole cell. In
summary, the invention provides a structure having a reduced
cell area because of reductions in area on both levels while
providing the transistor in conventional seam-free single
crystal semiconductor.
Claim 1, which is representative for our purposes,
follows:
1. A semiconductor structure, comprising
a device having a gate, said gate consisting of
an individual segment of gate conductor on a thin
gate dielectric, said device further comprising a
seam-free single crystal semiconductor substrate;
and
a connector on top of and electrically
contacting said segment gate conductor, said
connector being a conductive spacer rail extending
beyond said device.
The references relied on in rejecting the claims follow:
Dhong et al. (Dhong) 5,214,603 May 25,
1993
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