Appeal No. 1998-3331 Page 2
Application No. 08/852,842
Figure 2 of the appellants’ specification shows a
conventional multiprocessor system. The system comprises a
plurality of processors 70 having their own instruction and
data streams from corresponding memories 80. Each processor
can execute its own job instruction stream independently of
the other processors when no interaction with another
processor is required. An implementation in which one of the
processors assigns some of its tasks to another processor,
however, requires synchronization between the processors.
Such synchronization is usually accomplished using memory-
based locking. Specifically, only one access to any memory
location can occur in any memory cycle. As a result,
substantial bottlenecks are created during communications
between the processors.
In contrast, Figure 3 of the specification shows the
appellants’ multiprocessor architecture. A main DSP 100
resides on a main DSP chip; an auxiliary DSP 200 resides on a
filter processor chip. The main and auxiliary DSPs share data
memory 300; both DSPs can access all memory in the data space.
Although the main DSP’s program memory 102 and the auxiliary
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