Ex parte HEDAYAT et al. - Page 5




          Appeal No. 1998-3331                                       Page 5           
          Application No. 08/852,842                                                  


          that the examiner erred in rejecting claims 1, 2, 4-17, 19,                 
          and 20.  Accordingly, we reverse.                                           


               We begin by noting the following principles from In re                 
          Rijckaert, 9 F.3d 1531, 1532, 28 USPQ2d 1955, 1956 (Fed. Cir.               
          1993).                                                                      
               In rejecting claims under 35 U.S.C. Section 103, the                   
               examiner bears the initial burden of presenting a                      
               prima facie case of obviousness.  In re Oetiker, 977                   
               F.2d 1443, 1445, 24 USPQ2d 1443, 1444 (Fed. Cir.                       
               1992)....  "A prima facie case of obviousness is                       
               established when the teachings from the prior art                      
               itself would appear to have suggested the claimed                      
               subject matter to a person of ordinary skill in the                    
               art."  In re Bell, 991 F.2d 781, 782, 26 USPQ2d                        
               1529, 1531 (Fed. Cir. 1993) (quoting In re Rinehart,                   
               531 F.2d 1048, 1051, 189 USPQ 143, 147 (CCPA 1976)).                   

          With these principles in mind, we consider the examiner's                   
          rejection and the appellants' argument.                                     


               The examiner asserts, "Intrater et al. taught the                      
          invention substantially as claimed as claimed including a data              
          processing system comprising: a core processor (18); an                     
          auxiliary DSP (16) [sic]; a shared data memory (col. 47, lines              
          38- 49); a main program memory (16, co1.2, lines 55-65) and an              








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