Appeal No. 1999-0848
Application No. 08/634,310
a conductive plate on said recessed portion capacitively
coupled to said semiconductor body for enhancing breakdown
voltage of said p-n junction during device operation.
The Examiner relies on the following prior art:
Maeda et al. (Maeda) 5,442,226 Aug. 15,
1995
Jang 5,525,833 Jun.
11,
1996
(filed Jun. 07, 1995)
Nakano et al. (Nakano) 56-035462 Apr. 08,
1981
(Published Japanese Patent Application)1
Peter May and Frans C. Schiereck (May), “High-Speed Static
Programmable Logic Array in LOCMOS,” IEEE Journal of Solid-State
Circuits, Vol. SC-11, No. 3, 365-68 (June 1976).
Appealed claims 2-6, 8, and 10-12 stand rejected under
35 U.S.C. § 102 as anticipated by, or, in the alternative, under
35 U.S.C. § 103 as being obvious over, each one of the Nakano,
Maeda, Jang, and May references.
1A copy of a translation provided January 2001 by the U.S. Patent &
Trademark Office is included with this decision.
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