Appeal No. 2000-0312
Application No. 08/610,007
compensated . . . is a dc offset voltage internal to amplifier
(22),” and that the feedback circuit in Masuda does not
increment and decrement the feedback signal in the manner
required by the claimed invention. In short, we agree with the
appellants’ argument (reply brief, page 6) that the examiner has
resorted to impermissible hindsight to demonstrate the
obviousness of the claimed invention based upon the teachings
and suggestions of Masuda. Based upon the foregoing, the 35
U.S.C. § 103(a) rejection of claims 1 through 6, 8 through 14
and 16 through 22 based upon Masuda alone is reversed.
Turning lastly to the obviousness rejection of claims 1
through 22 based upon the combined teachings of appellants’
admitted prior art Figure 1 and Masuda, we agree with the
examiner’s observation (answer, page 4) that the processing
circuit in Figure 1 of Masuda does not disclose the claimed
feedback circuit. As indicated supra, the feedback circuit in
Masuda does not function in the manner required by the claims on
appeal. Thus, we agree with appellants’ argument (brief, page
15) that “[a]pplicants’ prior art circuit illustrated in FIG. 1
provides no motivation to a person of ordinary skill in the art
to utilize the Masuda feedback circuitry for any other reason
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