Ex Parte MIZUNO et al - Page 2




          Appeal No. 2000-0452                                                        
          Application No. 08/622,389                                                  

               According to appellants, the invention is directed to a                
          circuit, and a microcomputer including the circuit, by                      
          controlling power consumption of a semiconductor device by                  
          controlling the subthreshold leakage current in response to the             
          frequency of a reference signal.  The subthreshold leakage                  
          current is controlled by controlling the threshold voltage of               
          transistors of the semiconductor device.                                    
               The following claim is illustrative of the invention:                  
               1.  A semiconductor integrated circuit comprising:                     
                    a logic circuit which implements a certain logical                
               processing, the logic circuit including a unit logic                   
               circuit having two inputs and one output;                              
                    a control circuit which controls the threshold                    
               voltage of transistors that constitute said logic                      
               circuit; and                                                           
                    a first circuit whose delay characteristics can be                
               controlled,                                                            
                    said transistors of said logic circuit comprising                 
               MIS transistors, said first circuit delivering an                      
               output signal to said control circuit which also                       
               receives a reference signal, said control circuit                      
               producing a first and second control signals                           
               correspondent with said reference signal, said first                   
               control signal being fed to said first circuit, and                    
               said second control signal being fed to said MIS                       
               transistors of said logic circuit so as to vary power                  
               consumption and operation speed of said logic circuit                  
               in response to a frequency of said reference signal.                   




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