Appeal No. 2000-1251
Application No. 08/843,786
resetting the integrated circuit after the integrated circuit has
erroneously entered a test mode during normal operation as
recited in claim 12. In addition, the discussions in Miyawaki
also do not teach a method for protecting an IC against the
consequences of having erroneously entered a test mode during
normal operation comprising the step of resetting the IC based on
the receipt of the test mode start-up signal as recited in claim
20.
We note that columns 31-32 of Slemmer recognizes the problem
of an IC erroneously entering a test mode during normal
operation. This discussion in Slemmer centers on either a
complete shutdown of the system or using a chip enabling function
to deal with the consequences of the IC inadvertently entering
test mode during normal operation. In the complete shutdown
method, Slemmer is silent regarding whether the shutdown is
accomplished using a reset circuit responsive to a test mode
start-up signal, and we refuse to speculate. In the chip
enabling function method, Slemmer discloses in column 33, lines
6-9 that the possibility of entering test mode inadvertently
during normal operation is eliminated. Thus, upon review of
columns 31-32 of Slemmer, we find these methods do not provide a
teaching to include a reset circuit responsive to a test mode
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