Appeal No. 2001-0149
Application 08/896,001
1(a) in claim 1); an interconnect chip for coupling first and
second programmable logic devices (element 1(d) in claim 1). See
Examiner’s Answer, page 3, lines 16-19.
Appellant argues that the Examiner has not provided a
sufficient basis for rejecting the claims. Appellant asserts
that the Examiner’s arguments in the Final Office Action do not
take into account all the limitations of the claims. Appellant
states that the only independent claims in the application,
claims 1, 7, 10 and 17, variously include distinctions such as an
“interconnection chip associated with each logic device” designed
to provide communication of information between logic devices in
the same row or column. See Brief, page 3, lines 15-18.
In rejecting claims under U.S.C. § 103, the Examiner
bears the initial burden of establishing a prima facie case.
In re Oetiker, 977 F.2d 1443, 1445, 24 USPQ 1443, 1444 (Fed. Cir.
1992). See also In re Piasecki, 745 F.2d 1468, 1472, 223 USPQ
785, 788 (Fed. Cir. 1984). Only if this initial burden is met
does the burden of coming forward with evidence or argument shift
to the Appellants. Oetiker, 977 F.2d at 1445, 24 USPQ at 1444.
See also Piasecki, 745 F.2d at 1472, 223 USPQ at 788.
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