Appeal No. 2001-0149
Application 08/896,001
logic devices in a single column. Winlow does not include a
design of the interconnect chips coupled to an associated logic
device and to a vertical and horizontal conductor. Further,
Winlow fails to teach that the interconnect chip is associated
with each logic device in the array on a one-to-one basis.
In addition, there is no suggestion of arranging the
programmable logic devices in an array which are coupled by
horizontal conductors and vertical conductors. While arrays of
programmable logic devices are well known in the art and the
concept of connecting the element of an array by horizontal
and/or vertical conductors is also well known, there is no
suggestion to lead a person of ordinary skill in the art to
connect an interconnect chip associated with each logic device
in the array on a one-to-one basis and then connect vertical
conductors to the logic devices in rows in the array and
horizontal conductors to the logic devices in columns in the
array.
In conclusion, we find the Winlow reference fails to
disclose, teach or suggest an “interconnect chip associated
with each logic device” designed to provide communication of
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