Appeal No. 1999-0166
Application No. 08/656,544
(vi) wherein said clock selector selects said
system clock signal during normal operation and said test
clock signal during loading of program instructions
during test operation, said clock selector being
responsive to one or more clock selecting bits within
each program instruction
to be executed during said test operation to select
independently for each program instruction either said
test clock signal or said system clock signal for driving
said processor core to execute that program instruction,
said clock selector selecting said system clock signal to
drive operation of said processor core during test
operation to execute a program instruction from said
subset of program instructions such that operation of
said processor core is synchronized with said auxiliary
circuit.
The Examiner relies on the following prior art:
Antanaitis, Jr. et al. 5,163,146 Nov. 10,
1992
(Antanaitis)
Greenberger et al. 5,355,369
Oct. 11,
1994
(Greenberger) (filed Apr. 26,
1991)
Sakai et al. (Sakai) 5,479,645 Dec. 26,
1995
(filed Oct. 07,
1992)Ganapathy 5,561,792
Oct. 01, 1996
(effectively filed Dec.
28, 1992)
Claims 1 and 3-9 stand finally rejected under 35 U.S.C.
§ 103. As evidence of obviousness, the Examiner offers
Greenberger in view of Ganapathy and Sakai with respect to
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