Appeal No. 1999-1286
Application No. 08/567,950
The examiner concedes that Abe does not describe marking the defective
circuits at a plurality of locations. (Answer at 5.) To remedy this deficiency, the
examiner relies on Shils, which teaches marking at a plurality of locations in order to
write various information on the circuit to inform subsequent failure analysis. (Id., citing
Shils at col. 4, ll.40–60, col. 5, ll.1–20, and col. 6, ll.25–30.) Appellant objects that Shils
teaches away from destructive marking, because Shils teaches that the marking should
be done on the back of the chip, such that the marking does not impinge on chip real
estate. (Brief at 8–9, citing Shils at col. 2, ll.57–60.)
On review of Shils in its entirety, we agree with Appellant that Shils is concerned
exclusively with non-destructive marking, and thus provides no reason, suggestion,
teaching, or motivation for the combination with the teachings of Abe regarding
destructive marking proposed by the examiner. Accordingly, we hold that the examiner
has not established a prima facie case of obviousness based on the combined
teachings of Abe and Shils, and we reverse rejection 2.
The examiner relies in rejection 3 on Hidaka for teachings of focusing the
radiation to control a mark diameter. (Answer at 7.) Because Hidaka does not cure the
deficiency of Abe or Shils to teach or suggest multiple sites of destructive marking on
each defective integrated circuit, we also reverse rejection 3.
C. Decision
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