Appeal No. 1999-2701
Application No. 08/650,850
Ziperovich. In particular, the Examiner (Answer, page 3) points to
the structure illustrated in Figures 5A-5C, 8, and 9 of Ziperovich
along with the accompanying description beginning at column 11,
line 57.
Appellants’ arguments in response (Brief, page 6) focus on the
assertion that the Examiner has misinterpreted the disclosure of
Ziperovich as describing the claimed clock signal processing. In
particular, Appellants contend (id.) that, contrary to the claimed
clock signals, the inputs to the detector 50 and FIR filter 48 in
the Figure 9 circuit illustration in Ziperovich referenced by the
Examiner are read data signals.
After reviewing the Ziperovich reference in light of the
arguments of record, we are in general agreement with Appellants
that the inputs to the exclusive-OR logic circuit illustrated in
Figure 9 of Ziperovich are data signals, not clock signals. As
described beginning at column 4, line 1 of Ziperovich, the
disclosed write precompensation technique begins with the writing
of a predetermined tribit data pattern to a magnetic recording
medium. Equalized sample values of this tribit data pattern are
read back from a read channel and applied to a mean-squared error
(MSE) function block. The resulting accumulation of error values
of the read data signal samples are used to develop a minimum
4
Page: Previous 1 2 3 4 5 6 7 8 Next
Last modified: November 3, 2007