Appeal No. 1999-2701
Application No. 08/650,850
mean-squared error value corresponding to an optimal amount of
write precompensation. It is apparent to us from the description
of the write precompensation procedure in Ziperovich that the read
signals applied to the exclusive-OR MSE function block variation
illustrated in Ziperovich’s Figure 9, relied on by the Examiner to
address the claimed limitations, are pattern data signals and not
clock signals.
We are cognizant of the Examiner’s assertion in the response
to arguments portion of the Answer at page 4 that the disclosure of
Ziperovich indicates that clock signals are used to record and
reproduce information. In our view, however, the mere fact that
clock signals may be used in some fashion in the write
precompensation circuit of Ziperovich does not address the specific
language of the appealed independent claims 15 and 32 which
requires the formation of an extended duty cycle clock signal based
on the application of a clock signal and a delayed clock signal to
a logical OR operation.
We further note that both Appellants and the Examiner, in
support of their respective positions, make reference to the
passage at column 5, lines 5-11 of Ziperovich, which describes the
clock cycle spacing of a repeating recording pattern of tribit
signal pairs. Our interpretation of the significance of this
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