Appeal No. 2001-1189
Application No. 08/824,140
Reference is made to the briefs (paper numbers 18 and 22)
and the answer (paper number 21) for the respective positions of
the appellant and the examiner.
OPINION
We have carefully considered the entire record before us,
and we will reverse the obviousness rejection of claims 1, 2,
4 through 10, 12 through 18 and 20 through 27.
According to the examiner (answer, pages 3 and 4), Lyon
discloses (prior art Figure 1a) “a dynamic logic circuit operable
for reset during a precharge clock phase (when CLK is low) and to
evaluate during an evaluate clock phase (when CLK is high),
comprising: a first NFET (13a) coupled in series between a first
node and a first reference voltage (ground) wherein gate
electrode of the first NFET is operable for receiving a data
input (InA); a third NFET (12) coupled between the NFET and a
reference voltage (ground) and receiving a clock signal (CLK).”
The examiner acknowledges (answer, page 4) that “Lyon’s prior art
figure 1 does not teach the claimed second NFET and first
PFET . . . . ” The examiner additionally states (answer, page 4)
that:
In figure 4, D’Souza shows a standard MOS logic
structure wherein the typical parallel pull-down N-
channel MOSFETs are replaced by 2 NFETs and 1 PFET
3
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