Appeal No. 2001-1189
Application No. 08/824,140
connected identically as the claimed first and second
NFETs and first PFET. This three transistor structure
is an input switch structure receiving a signal input.
It is taught as improving the output signal levels of
the logic circuitry it is applied to and as reducing
leakage current (see, for example, column 1, line 65 -
column 2, line 9).
Based upon the teachings of the applied references, the examiner
concludes (answer, page 4) that “it would have been obvious to
one of ordinary skill in the art at the time of appellant’s
invention to have replaced the input transistor (13a) of the
dynamic MOS logic circuit of Lyon’s prior art figure 1 with the
three transistor structure (i.e.[,] 422a, 424a, 426a of figure
4) as taught by D’Souza in order to provide a dynamic MOS logic
circuit with improved output signal levels and lower leakage
current.”
Appellant argues (reply brief, pages 2 through 6, 9 and 10)
that Lyon is directed to dynamic logic circuits, whereas D’Souza
is directed to static logic circuits, and that the skilled
artisan would not resort to the static logic teachings of D’Souza
to modify the dynamic logic teachings of Lyon. To be more
specific, appellant argues (reply brief, page 5) that “the
Examiner has not provided objective evidence that the teaching in
D’Souza does function in a dynamic logic circuit, such as that
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