Appeal No. 2001-2503
Application No. 09/075,767
APPEALED SUBJECT MATTER
The subject matter on appeal is directed toward a method of forming a semiconductor
device comprising a fuse and an integrated circuit wherein a contact pad is formed above the
integrated circuit. See e.g., claims 1, 15 and 35. The method involves, inter alia, patterning an
anti-reflective coating formed on the contact pad while simultaneously removing a dielectric
material that was deposited over the fuse. Id. This method requires that the anti-reflective
coating and the dielectric material be etched at “substantially the same rate”, i.e., an etch rate
selectivity of approximately 1:1. See e.g., claims 1, 15 and 35, together with the specification,
page 6. “Substantially the same rate” is defined as providing the dielectric material with an etch
rate within 20% of the etch rate of the anti-reflective coating. See the specification, page 6.
The etch rate selectivity results in exposing the contact pad without exposing the fuse covered
with the dielectric material. See, e.g., claims 1, 15 and 35. Additional details of the claimed
subject matter are provided in representative claims 1, 15 and 35 below:
1. A method for forming an integrated circuit comprising the steps of:
providing a semiconductor substrate;
forming a first conductive layer overlying the semiconductor substrate;
removing a portion of the first conductive layer to define a fuse and a conductive
interconnect;
forming a first dielectric layer overlying the fuse and the conductive interconnect;
forming a bonding pad overlying the first dielectric layer, wherein the bonding pad
comprises an anti-reflective layer overlying a second conductive layer, and wherein the bonding
pad is electrically shorted to the conductive interconnect;
forming a second dielectric layer overlying the fuse and the bonding pad;
2
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