Appeal No. 2001-2503
Application No. 09/075,767
etching the second dielectric layer using a first etch process to form an exposed portion
of the first dielectric layer and to form an exposed portion of the anti-reflective layer, wherein
the exposed portion of the first dielectric layer overlies the fuse, and wherein the second
conductive layer is not exposed by the first etch process; and
etching the exposed portion of the anti-reflective layer and the exposed portion of the
first dielectric layer using a second etch process to leave a remaining portion of the first
dielectric layer overlying the fuse and to expose a portion of the second conductive layer, the
exposed portion of the anti-reflective layer having a first etch rate and the exposed portion of the
first dielectric layer having a second etch rate, wherein the first etch rate and the second etch rate
are substantially the same such that an etch selectivity of approximately 1:1 is achieved between
the exposed portion of the anti-reflective layer and the exposed portion of the first dielectric
layer.
15. A method for forming an integrated circuit comprising the steps of:
providing a semiconductor substrate;
forming a fuse overlying the semiconductor substrate;
forming a first dielectric layer overlying the fuse;
forming a bonding pad overlying the first dielectric layer, wherein the
bonding pad comprises an anti-reflective layer overlying a conductive layer; and
etching a portion of the anti-reflective layer and a portion of the first dielectric layer to
leave a remaining portion of the first dielectric layer overlying the fuse and to expose a portion
of the conductive layer, the anti-reflective layer having a first etch rate and the first dielectric
layer having a second etch rate, wherein the first etch rate and the second etch rate are
substantially the same such that an etch selectivity of approximately 1:1 is achieved between the
anti-reflective layer and the first dielectric layer.
35. A method for forming an integrated circuit comprising the steps of:
providing a semiconductor substrate;
forming a fuse overlying the semiconductor substrate;
forming a first dielectric layer overlying the fuse;
forming a bonding pad overlying the first dielectric layer, wherein the
bonding pad comprises an anti-reflective layer overlying a conductive layer; and
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