Appeal No. 2001-2660
Application 09/392,341
Representative claim 1 is reproduced below:
1. A switching circuit comprising:
a CMOS inverter having an input terminal coupled to a node,
an output terminal, and comprising a nMOSFET;
a domino logic gate having an output terminal coupled to the
node to drive the node HIGH and LOW;
a pullup pMOSFET having a gate at a logic level equal to the
logic level of the CMOS inverter output terminal and having a
drain coupled to the node to provide a half latch function to
latch the node HIGH only when the node is brought HIGH; and
a bias circuit coupled to ground and to the CMOS inverter
nMOSFET to increase the threshold voltage of the CMOS inverter
nMOSFET compared to when its substrate and source are both at
ground potential.
The following references are relied on by the examiner:
Magee 4,578,600 Mar. 25, 1986
Appellants' admitted prior art Figure 1
Claims 1, 2, 4, 5, and 8-13 stand rejected under 35 U.S.C.
§ 103. As evidence of obviousness, the examiner relies upon
appellants' admitted prior art Figure 1 in view of Magee.
Rather than repeat the positions of the appellants and the
examiner, reference is made to the brief and the answer for the
respective details thereof.
2
Page: Previous 1 2 3 4 5 6 7 8 9 Next
Last modified: November 3, 2007