Appeal No. 2002-0590
Application No. 09/213,924
BACKGROUND
Appellant's invention relates to a synchronized signal transfer system. An
understanding of the invention can be derived from a reading of exemplary claim 1,
which is reproduced below.
1. A memory system comprising:
a memory controller;
a first memory device;
a first data bus for transporting data between the memory controller and
the first memory device;
a first clock bus, carrying a first clock signal, for facilitating a transfer of the
data from the memory controller to the first memory device; and
a second clock bus, carrying a second clock signal, facilitating a transfer
of the data from the first memory device to the memory controller, wherein the first and
second clock buses are separate buses, wherein the first and second clock signals are
separately generated.
The prior art references of record relied upon by the examiner in rejecting the
appealed claims are:
Gasbarro et al. (Gasbarro) 5,432,823 Jul. 11, 1995
Niu et al. (Niu) 6,161,160 Dec. 12, 2000
(Filed Sep. 3, 1998)
Claims 1-42 stand rejected under 35 U.S.C. § 103 as being unpatentable over
Gasbarro in view of Niu.
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