Appeal No. 2003-1690
Application 09/635,061
THE REJECTIONS
The claims stand rejected under 35 U.S.C. § 103 as follows:
claims 24 and 26 over Makita in view of Ipri; claims 25 and 27
over Makita in view of Ipri and Nam; and claims 28 and 29 over
Makita in view of Ipri and Lee.
OPINION
We reverse the aforementioned rejections. We need to
address only the sole independent claim, i.e., claim 24.1
The examiner relies upon Makita’s disclosure related to
figures 7A-7F (answer, page 5). In this disclosure Makita sets
forth a process for manufacturing a thin film transistor,
comprising depositing a semiconductor layer (503) on a substrate
(501, covered by silicon oxide film 502) by plasma CVD (col. 28,
lines 55-56), depositing a gate dielectric layer (507) by
plasma CVD consecutively to the step of depositing the
semiconductor layer (col. 28, lines 48-54), patterning the
semiconductor layer together with the gate dielectric layer into
an island shape (col. 29, lines 52-57; figure 7D), depositing a
conductor layer over the gate dielectric layer, and patterning
1 The examiner does not rely upon Nam or Lee for a
disclosure which remedies the deficiency in Makita and Ipri as to
claim 24.
3
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