Ex Parte BRYANT - Page 7


               Appeal No. 2003-2130                                                                                                   
               Application 08/159,461                                                                                                 

               the gate electrode” (reply brief, page 4).                                                                             
                       In following the method steps disclosed in col. 4 of Geipel, we find that subsequent to the                    
               deposition of phosphorous doped polysilicon over the 150 to 800 angstroms of silicon dioxide                           
               which provides the gate insulating layer,                                                                              
                    the last deposited layer of polysilicon is etched to form IGFET gate electrodes.                                  
                    Retaining or removing and regrowing the gate dielectric over remaining portions of                                
                    the substrate to act as an ion implantation screen in the next step is optional at this                           
                    point.                                                                                                            
                       Source and drain regions are next formed by ion implantation/drive in process using                            
                    both the polysilicon and [semi-recessed dielectric oxide] areas as a mask. [Col. 4, lines                         
                    35-60; emphasis supplied.]                                                                                        
                       In comparing the methods steps of Geipel with the limitations in claim 66 that we set                          
               forth above, it is readily apparent that it is the step of “regrowing the gate electrode over the                      
               remaining portions of the substrate” prior to the formation of source and drain regions in Geipel                      
               which corresponds in certain respects to the claimed “reoxidizing” step.  The deficiency in this                       
               reference disclosure with respect to the claim limitations is two fold as appellant points out.                        
               First, there is no teaching to “regrow” the gate oxide over all of the exposed surfaces of the                         
               patterned substrate, which includes the polysilicon layer.  And, second, there is no teaching of the                   
               thickness of the “regrown” gate oxide on the exposed substrate.  With respect to the latter, the                       
               examiner’s inherency theory is untenable because it is based on further disclosure at col. 6, lines                    
               22-26, which involves a step in a “preferred process related specifically to the source drain                          
               junction formation” (col. 6, lines 8-9; see also col. 4, line 60, to col. 5, line 1, and col. 6, lines                 
               11-21; and the Office action of November 30, 2001, Paper No. 33, page 3, last three lines of the                       
               fourth full paragraph) and not the “regrowing” step.                                                                   
                       Accordingly, on this record, we reverse the ground of rejection under 35 U.S.C. § 103(a).                      
                       The examiner’s decision is reversed.                                                                           








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