Ex Parte Vikram et al - Page 1



                  The opinion in support of the decision being entered                
                       today was not written for publication and                      
                         is not binding precedent of the Board.                       
                                                            Paper No. 15              
                      UNITED STATES PATENT AND TRADEMARK OFFICE                       
                                    _____________                                     
                         BEFORE THE BOARD OF PATENT APPEALS                           
                                  AND INTERFERENCES                                   
                                    _____________                                     
                  Ex parte SESHADRI VIKRAM and WILLIAM J. SCHAEFER                    
                                   _____________                                      
                                Appeal No. 2004-0133                                  
                             Application No. 09/668,031                               
                                   ______________                                     
                                      ON BRIEF                                        
                                   _______________                                    
          Before KIMLIN, GARRIS and STAAB, Administrative Patent Judges.              
          KIMLIN, Administrative Patent Judge.                                        
                                 DECISION ON APPEAL                                   
               This is an appeal from the final rejection of claims 1-3,              
          5, 7-9, 11 and 12, all of the claims remaining in the present               
          application.                                                                
               Claim 1 is illustrative:                                               
               1.   A packaged integrated circuit comprising:                         
                    a die having first and second surfaces and a                      
               multiplicity of die contacts arranged on the first                     
               surface of the die;                                                    
                    a barrier layer deposited on the second surface of                
               the die;                                                               





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