Appeal No. 2004-0573
Application No. 09/406,017
Appellants’ invention relates to a method and apparatus for a simulation monitor
that detects and reports a status event to a database. An understanding of the
invention can be derived from a reading of exemplary claim 1, which is reproduced
below.
1. A monitor that detects a design verification event and reports a
status event to a database, comprising:
a monitor declaration;
zero or more signal declarations wherein an individual signal
declaration describes a signal having a signal name;
zero or more bus declarations wherein said bus declaration defines
a bus that further comprises a set of signals that represents a single value
determined by packing single bit values into a multibit variable; and
one or more logic expressions that the monitor uses to evaluate
whether the design verification event has occurred so that the monitor can
return a status event.
The prior art of record relied upon by the examiner in rejecting the appealed
claims is as follows:
Giramma 5,706,476 Jan. 6, 1998
Rostoker et al. (Rostoker) 5,867,399 Feb. 2, 1999
Rajan, S., “Essential VHDL: RTL Systhesis Done Right,” Chapters 2 and 8, pp 13-23,
141-165 (Copyright 1997)
2
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