Appeal No. 2004-0593
Application No. 09/606,688
in another group (Appeal Brief, page 7, lines 15-18), claims 4,
10, and 16 as a third group (Appeal Brief, page 7, lines 19-21),
while claims 27, 31, 35, and 39 appear to be argued in yet another
group. (Appeal Brief, page 9, lines 6-8). Accordingly, we select
claims 1, 3, 4, and 27 as representative of the claims on appeal.
Note In re Dance, 160 F.3d 1339, 1340 n.2, 48 USPQ2d 1635, 1636
n.2 (Fed. Cir. 1998); In re King, 801 F.2d 1324, 1325, 231 USPQ
136, 137 (Fed. Cir. 1986); In re Sernaker, 702 F.2d 989, 991, 217
USPQ 1, 3 (Fed. Cir. 1983).
These claims read as follows:
1. A buffer/voltage-mirror arrangement comprising:
a plurality of stages, each comprising:
electrically parallel branches of a first transistor
connected in series with a second transistor, and a third
transistor connected in series with a fourth transistor, said
second and fourth transistors being of an inverse type to that of
said first and third transistors, where said first and third
transistors are substantially matched and said second and fourth
transistors are substantially matched, a gate interconnection
electrically connecting gates of said first and second transistors
to one another, and an intermediate electrical connection directly
connecting all of the gates of said third and fourth transistors,
an intermediate point between said first and second transistors
and an intermediate point between said third and fourth
transistors to one another;
wherein said gate interconnection of a first stage represents
an input, wherein said intermediate electrical connection of a
preceding stage is electrically connected to said gate
interconnection of a succeeding stage, and said intermediate
electrical connection of a final stage represents an output, and
wherein said buffer/voltage-mirror arrangement is adapted to cause
an output voltage on said output to mirror an input voltage on
said input by a predetermined factor.
2
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