Appeal No. 2004-0593
Application No. 09/606,688
3. A buffer/voltage-mirror arrangement as claimed in claim
1, wherein ones of said first, second, third and fourth
transistors of an input stage of said buffer/voltage-mirror
arrangement are smaller in size than other ones of said first,
second, third and fourth transistors of other stages so as to
minimize an influence of said buffer/voltage-mirror arrangement on
any input circuit to which said buffer/voltage-mirror arrangement
is attached.
4. A buffer/voltage-mirror arrangement as claimed in claim
1, wherein ones of said first, second, third and fourth
transistors of an output stage of said buffer/voltage-mirror
arrangement are larger in size than other ones of said first,
second, third and fourth transistors of other stages so as to
increase a driving capacity of said buffer/voltage-mirror
arrangement.
27. A buffer/voltage-mirror arrangement as claimed in claim
1, wherein said a plurality of stages are arranged in a non-
feedback, series cascade of stages.
The Reference
In rejecting the claims under 35 U.S.C. §102(b), the examiner
relies upon the following reference:
Rempfer et al. (Rempfer) 5,070,259 Dec. 03, 1991
The Rejection
Claims 1-4, 7-10, 13-16, 25, 27, 31, 35, and 39 stand
rejected under 35 U.S.C. §102(b) as being anticipated by Rempfer.
The Invention
The invention relates to a buffer/voltage-mirror circuit for
use in, e.g., automated test equipment. (Specification, page 1,
lines 2-3 and 14). The circuit is designed to provide
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