Ex Parte Subramanian - Page 7




             Appeal No. 2004-1834                                                                              
             Application No. 10/158,885                                                                        

                   Specifically, appellant argues that Balamurugan allows the local fab to find the            
             dies to be picked using a wafer map “without the many steps” of Balamurugan “to                   
             determine using a whole wafer map where the locator die is” (reply brief-page 4).  The            
             language of claim 1 relied on is “identifying a pseudo reference die for each partial             
             wafer not having a reference die which die is the first die in the bottom right.”  Appellant      
             contends that in the reference the auxiliary reference die row is always in the reference         
             die row (column 5, lines 36-37), which requires information on where the reference die            
             is.  Thus, according to appellant, in Balamurugan, if there is no reference die and the           
             location of the reference die is not known, Balamurugan’s method cannot determine                 
             where the auxiliary die is located.  The present invention does not have to know where            
             the reference die is located because it uses the pseudo reference die which is the first          
             die on the bottom right or the next die column number after the last column number of             
             the previous partial wafer.                                                                       
                   Notwithstanding arguments that may be directed to the instant disclosed                     
             invention, Appellant is arguing the claim 1 language, “identifying a pseudo reference die         
             for each partial wafer not having a reference die which die is the first die in the bottom        
             right.”  But Balamurugan clearly states that a “reference die is located in the first partial     
             wafer P1 and an auxiliary reference die is located in other partial wafers P2 to P5 in the        
             lower right corner on the same row as the reference die” (column 4, lines                         




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