Appeal No. 2005-0237
Application No. 10/165,861
chosen to control the depth of features formed in the surface of
the substrate after the etching delay layer is removed and the
substrate is etched by the etching process. This appealed
subject matter is adequately represented by independent claim 1
which reads as follows:
1. A method for fabrication of silicon-based
microstructures, comprising the deposition and patterning of an
etching delay layer on a surface of a substrate, and further
comprising an etching process, the thickness and location of said
etching delay layer being chosen to control the depth of features
formed in the surface of the substrate after said etching delay
layer is removed and the substrate is etched by said etching
process.
The references set forth below are relied upon by the
examiner as evidence of anticipation and obviousness:
Bohannon et al. (Bohannon) 5,348,619 Sep. 20, 1994
Bastani et al. (Bastani) 5,554,554 Sep. 10, 1996
IBM Technical Disclosure Bulletin (IBM), NB82081402, pp. 1402-
1403, August 1982.
Claims 1 and 2 are rejected under 35 U.S.C. § 102(b) as
being anticipated by the IBM reference.
Claims 1-3 and 5 are rejected under 35 U.S.C. § 102(b) as
being anticipated by Bohannon.
Finally, claim 4 is rejected under 35 U.S.C. § 103(a) as
being unpatentable over Bohannon in view of Bastani.
Rather than reiterate the respective positions advocated by
the appellants and by the examiner concerning the above noted
2
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