Ex Parte Mehrotra et al - Page 5



         Appeal No. 2005-0239                                                       
         Application No. 10/145,421                                                 

         advanced by both the examiner and the appellants in support of             
         their respective positions.  This review has led us to conclude            
         that only the examiner’s Section 103 rejections are well founded.          
         Accordingly, we affirm the examiner’s Section 103 rejections, but          
         reverse the examiner’s Section 102 rejection.  We also set forth           
         a new ground of rejection against claims 1 and 5.  Our reasons             
         for these determinations follow.                                           
                         35 U.S.C. § 102(e) (ANTICIPATION)                          
              Under Section 102, the claimed subject matter is said to be           
         anticipated only when a single prior art reference discloses,              
         either expressly or under the principles of inherency, each and            
         every element of a claimed invention.  See In re Spada, 911 F.2d           
         705, 708, 15 USPQ2d 1655, 1657 (Fed. Cir. 1990); RCA Corp. v.              
         Applied Digital Data Systems, Inc., 730 F.2d 1440, 1444, 221 USPQ          
         385, 388 (Fed. Cir. 1984).                                                 
              According to the examiner (Answer, page 3), Lin teaches all           
         aspects of the claimed subject matter.  Specifically, the                  
         examiner asserts that:                                                     
              Lin et al. teach a method of producing an integrated                  
              circuit comprising the steps providing a semiconductor                
              substrate 10; forming a gate dielectric 20 on an active               
              area on the substrate; depositing a polysilicon layer                 
              30 on top of the gate dielectric; implanting a first                  
              dopant into the gate (see Fig. 1A); patterning a second               
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