Ex Parte Ansari - Page 11




                 Appeal No. 2005-2273                                                                                 Page 11                     
                 Application No. 10/319,026                                                                                                       



                 Inside Out (rev. ed. 1986).  As found by the examiner, (Examiner's Answer at 5), Karp                                            
                 teaches the following limitations of claim 21:                                                                                   
                 A circuit                                                  fig. 1                                                                
                 comprising a microprocessor,                               22                                                                    
                 the microprocessor comprising:                                                                                                   
                 a register file comprising a plurality of registers        fig. 2, 58, 42, 43, col. 2 lines 52-57                                
                 for                                                                                                                              
                 storing vector data                                                                                                              
                 a vector transfer unit                                     60-62, 50-52, 64-66                                                   
                 [c]oupled to the register file                             58, 42, 43                                                            
                 wherein the vector transfer unit comprises a               50, 51, 52, each buffer showing an                                    
                 dual port memory for storing vector data and               both an incoming and outgoing                                         
                                                                            port, two ports equaling "dual port"                                  
                 a vector transfer execution unit coupled to the            70, 71, 72                                                            
                 dual port memory                                                                                                                 
                 wherein the vector transfer execution unit                 col. 4 lines 50-60, the disclosed                                     
                 operates upon load/store and move vector                   "vector request instructions"                                         
                 data instructions                                          covers load, store, and move.                                         
                 wherein the vector transfer execution unit                 70, 71, 72                                                            
                 transfers vector data between a main memory                46, col. 6 line 48 to col. 8 line 7                                   
                 and                                                                                                                              
                 the dual port memory                                       50, 51, 52                                                            
                 in response to the vector transfer execution               70, 71, 72                                                            
                 unit                                                                                                                             
                 executing a load/store vector data instruction col. 4 lines 50-60                                                                
                 wherein the vector transfer execution unit                 70, 71, 72                                                            
                 transfer[s] vector data between the dual port              50, 51, 52                                                            
                 memory                                                                                                                           
                 and one or more registers of the register file             58, 42, 43                                                            
                 in response to the vector transfer execution               col. 4 lines 50-60                                                    
                 unit executing a move vector data instruction                                                                                    













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