Appeal No. 2006-1176
Application No. 09/926,202
according to claim 6, wherein a substrate resistivity of the
epitaxial wafer is 0.02 Ω-cm or lower.
PRIOR ART REFERENCES
The prior art references relied upon by the examiner are:
Wijaranakula et al. (Wijaranakula) 5,418,855 Mar. 18, 1997
Wolf et al. (Wolf), Silicon Processing for the VLSI Era, Volume
1: Process Technology, Lattice Press, Sunset Beach, California,
pp. 26-30 and 59-61, 124, 133-136 (1986).
REJECTION
Claims 6 through 21 stand rejected under 35 U.S.C. § 103(a)
as unpatentable over the combined disclosures of Wijaranakula and
Wolf.
OPINION
We have carefully reviewed the claims, specification and
applied prior art, including all of the arguments advanced by the
examiner and the appellant in support of their respective
positions. This review has led us to conclude the examiner’s
Section 103 rejection is well founded. Accordingly, we affirm
the examiner’s Section 103 rejection for essentially the reasons
set forth in the Brief and below. We add the following primarily
for emphasis and completeness.
The examiner finds (the Answer, page 4), and the appellant
does not dispute (the Brief, page 5) that Wijaranakula describes
3
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