Appeal No. 2006-1204
Application No. 10/379,006
clocks.
Now the question before us is what Mooney would have taught
to one of ordinary skill in the art? To answer this question, we
find the following facts:
1. Mooney states at column 5, lines 4-25 that:
As illustrated, an externally derived clock signal
drives the control circuit; however, it is divided
down by divider 442. Output buffer 320 comprises an
interface circuit output buffer, while output buffer
330 comprises a non-data signal or “dummy” output
buffer. A feedback control loop including amplifier
360 and impedance control logic 310 is coupled to
adjust the impedance of output buffer 330 based, at
least in part, on the impedance of external coupling
340. The feedback control circuit operates to
approximately match the impedance of buffer 330 with,
in this particular embodiment, the impedance of
external resistor 340. Likewise, in this embodiment,
resistors 370 and 350 effectively establish the voltage
signal reference level for amplifier 360. Impedance
control logic 310 based, at least in part, on the
output signal of amplifier 360 controls whether to
adjust the impedance of buffer 330 up or down, that is
increase or decrease the buffer impedance. Likewise,
this control signal information is also applied to
buffer 320. The feedback control circuit also produces
control signals to adjust the slew rate of buffer 320
based on the impedance control signals produced from
operation of the feedback loop including buffer 330.
With the above discussion in mind, we find that Mooney
teaches an externally derived clock signal that drives an
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