Appeal 2007-0157
Application 10/984,584
This is a decision on appeal under 35 U.S.C. § 134 from the Examiner's
final rejection of claims 1-4, 6-11, 15, 21, 22, 24-28, and 30. Claims 16-20
are indicated as allowable over the prior art and upon the filing of a
Terminal Disclaimer. Claims 5, 12-14, 23, and 29 are objected to as
depending from a rejected claim and would be allowable upon the filing of a
Terminal Disclaimer.
We AFFIRM.
BACKGROUND
Appellant's invention relates to a buffer/voltage-mirror arrangement for
sensitive node voltage connections. An understanding of the invention can
be derived from a reading of exemplary claim 1, which is reproduced below.
1. A buffer circuit comprising:
an input stage comprising electrically-parallel branches of a
first transistor connected in series with a second transistor, and
a third transistor connected in series with a fourth transistor,
said second and fourth transistors being of an inverse type to
that of said first and third transistors, a gate interconnection
electrically connecting gates of said first and second transistors
to one another, and an intermediate electrical connection
connecting all of the gates of said third and fourth transistors,
an intermediate point between said first and second transistors
and an intermediate point between said third and fourth
transistors to one another, wherein said first and third
transistors have width-to-length ratios which are substantially
equal to one another, and said second and fourth transistors
have width-to-length ratios which are substantially equal to one
another;
an output stage comprising electrically-parallel branches of
a first transistor connected in series with a second transistor,
2
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