Appeal 2007-0157
Application 10/984,584
and a third transistor connected in series with a fourth
transistor, said second and fourth transistors being of an inverse
type to that of said first and third transistors, a gate
interconnection electrically connecting gates of said first and
second transistors to one another, and an intermediate electrical
connection connecting all of the gates of said third and fourth
transistors, an intermediate point between said first and second
transistors and an intermediate point between said third and
fourth transistors to one another, wherein said first and third
transistors have width-to-length ratios which are substantially
equal to one another, and said second and fourth transistors
have width-to-length ratios which are substantially equal to one
another; and
wherein:
said gate interconnection of said input stage is coupled to an
input voltage;
said intermediate electrical connection of said input stage is
coupled to said gate interconnection of said output stage; and
said intermediate electrical connection of said output stage
is coupled to an output voltage that substantially mirrors said
input voltage by a predetermined factor.
PRIOR ART
The prior art references of record relied upon by the Examiner in
rejecting the appealed claims are:
Hsu US 3,946,327 Mar. 23, 1976
Song US 6,847,236 B1 Jan. 25, 2005
Hodges et al. (Hodges), Analysis and Design of Digital Integrated Circuits,
McGraw-Hill Inc., 1988, 2nd edition, section 10.5.4, 408-409.
Appellant’s Admitted Prior Art, Figure 1 (AAPA)
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