Appeal 2007-1552
Application 09/852,123
3. The base and emitter regions/gates are effectively short-circuited with
each other and connected to reference line 22 via the semiconductor substrate 12
and electrode 24 (Avery, Fig. 4, and col. 5, ll. 37-41).
4. The lightly-doped substrate 12 provides the emitter-base shunt
resistance RS (Avery, Fig.7, col. 5, ll. 42-44, and col. 6, ll. 44-46).
5. Avery further teaches the ESD structure includes at least one emitter
zone 42 and at least one collector zone 44 of a first conduction type N, at least one
base zone 58 of a second conduction type P, and a well-shaped region 56 of the
first conduction type N (Avery, Fig. 4, col. 5, ll. 10-15 and col. 5, ll. 47-51).
6. Smith teaches a semiconductor device having a stacked-gate buffer
that inhibits parasitic bipolar effects during electrostatic discharge or electrical
overstress (Smith, col. 1, ll. 6-10).
7. Smith teaches a well-shaped region 80 which inhibits the initiation of
bipolar action by creating a blocking of, or a long path for, avalanche generated
holes needed in order to forward bias the parasitic bipolar transistor formed by the
transistors 95 and 105 (Smith, Fig. 7 and col. 8, ll. 42-50).
8. The term “track resistor” does not have a customary meaning in the
art.
9. Appellants point to page 4, lines 8-9 [sic, lines 7-8] and page 7, lines
16-19 of the Specification for a discussion of the claimed single track resistor
(Appeal Br. 5). The cited passages state (1) “[a] single track resistor is co-
integrated into the semiconductor body and precedes every control connection of
the bipolar transistors,” and (2) “the base connections B of the bipolar transistors
5
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