Appeal 2007-1756
Application 10/185,476
network processor memory. Further, we do not find that Kale’s teaching of
the descriptor head and tail pointers being updated in the network processor
memory and written to the host processor memory necessarily teaches that
the value is written to both memories with one instruction. We find no
suggestion in Kale that this updating and writing be performed with one
instruction and, given that they are referred to as two types of operations
(updating and writing), we find no suggestion or indication that they
inherently are performed by one instruction. Thus, Appellant’s contention
has persuaded us of error in the Examiner’s rejection of independent claims
1, 19 and 40.
On the second issue, we disagree with Appellant’s assertion that Kale
does not teach one storage that can be written to by two processors.
Independent claim 35 recites “a storage coupled to said general purpose
processor to be written with data associated with a network message by a
network processor and by said general purpose processor, said network
processor coupled to said general purpose processor-based system by the
host bus.” Thus the scope of claim 35 includes that there is one storage that
can be written to by both the network processor and the host processor. As
discussed in our findings of fact, Kale teaches that the host processor
memory contains a list of host descriptor pointers. (Fact 5). This memory is
written to by the host processor which makes up descriptor pointers. (Fact
5). Kale also teaches that the network processor writes to the host memory
descriptor pointers as it is executing the descriptors. (Fact 7). Thus, we find
based upon the descriptor identified by the descriptor head portion and not
the tail portion.
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