Appeal No. 96-2379
Application 07/837,240
dithering value to take advantage of the carry bit to accomplish
any needed incrementation. This procedure saves processing time
and circuitry as compared to prior art which requires a
comparison operation for the fractional bits.
Like the appellant's claimed invention, Comins' technique
eliminates the need to compare the fractional bits to values in a
dithering matrix. In the argument portion of the appellant's
brief at 16-17, the appellant acknowledges that in Comins, the
least significant bits in the calculated pixel value are added to
a dithering value in a first adder 264, and any carry bit is
added to the more significant bits of the calculated pixel value
in a second adder 265 (Figure 2). No comparison of the
fractional or least significant bits of the input word or
calculated pixel value with any stored value is required.
With respect to claims 1 and 12, it is true that Figure 2 of
Comins does not disclose an interpolator register which
"receives" a dithering value to be added to any portion of the
calculated pixel value. Rather, a pseudo number PN generator 261
including a shift register is used to generate and output such a
dithering value (Figure 2). We agree with the examiner, however,
that registers are well known and are basic devices for storing
and holding data (answer at 4-5), and thus it would have been
5
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