Appeal No. 96-2379
Application 07/837,240
obvious to one with ordinary skill in the art to receive or
buffer between digital circuit stages a generated dithering value
in a holding or interpolator register prior to further
processing. Alternatively, the shift register in the PN
generator can be reasonably regarded as the claimed interpolator
register, because it holds the dithering value before outputting
the same to adder 264. We note that during patent examination,
claim terms are properly interpreted according to their broadest
reasonable interpretation consistent with the specification. In
re Zletz, 893 F.2d 319, 321, 13 USPQ2d 1320, 1322 (Fed. Cir.
1989); In re Yamamoto, 740 F.2d 1569, 1571, 222 USPQ 934, 936
(Fed. Cir. 1984); In re Pearson, 494 F.2d 1399, 1404, 181 USPQ
641, 645 (CCPA 1974); In re Prater, 415 F.2d 1393, 1404, 162 USPQ
541, 550 (CCPA 1969). Generating and holding is reasonably
deemed one form of receiving. At a minimum, it reasonably
suggests receiving.
Further with respect to claims 1 and 12, it is true that
Figure 2 does not illustrate an output register coupled to the
adder for receiving a selected number of bits of the resultant
value. Instead, the second adder 265 directly provides the
output. However, as the examiner correctly found, registers are
well known and are basic devices for storing and holding data.
6
Page: Previous 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Next
Last modified: November 3, 2007