Appeal No. 96-1207
Application No. 08/064,203
of the disclosure that states that "[t]he process of the
present invention has been found to increase the total charge
conducted through the dielectric layer by at least one order
of magnitude before catastrophic breakdown, while at the same
time providing a dramatic improvement in processing yields"
(specification, pages 6 and 7). In paragraph 20 of this same
declaration, declarant states that:
I consider the annealing process developed by
Vasche as being a very important aspect of his
invention. As is explained in the specification at
page 6, the unique annealing process results in a TEOS
oxide layer with substantially improved dielecric
properties, better leakage properties and better
breakdown properties than what was known in the prior
art. The improvements that were realized in respect to
these properties by performing a new annealing process
were completely different from what was known in the
prior [art]. In my opinion, these results were truly
surprising.
Paragraph 6 in the Exhibit B declaration states that:
[T]he devices claimed in the present invention all
use
the CVD deposited layer as a tunneling layer (i.e., a
layer through which tunneling electrons flow to program
or erase the floating gate), not simply as a[n]
insulating layer. As I pointed out in my prior
Declaration, such a tunneling layer must have both good
insulating properties and good tunneling properties to
be useful in a floating gate memory device. The
present patent application teaches the surprising
result that a properly deposited and annealed TEOS
6
Page: Previous 1 2 3 4 5 6 7 8 9 10 11 12 Next
Last modified: November 3, 2007