Ex parte TAKAHASHI et al. - Page 3




               Appeal No. 96-1727                                                                                                  
               Application 08/130,575                                                                                              



                                                            OPINION                                                                
                       Because we have difficulty in following the examiner’s correlation of the claimed                           
               features to Nishi, difficulty in agreeing with the examiner, and in part due to our agreement                       
               with some of appellants’ views as to this correlation, we reverse the outstanding rejection                         
               of all claims on appeal under 35 U.S.C. § 102 as set forth by the examiner.  However, we                            
               institute our own rejection under the provision of 37 CFR                                                           
               § 1.196(b) as set forth below.                                                                                      
                       Claims 1, 4, 8, and 9 are rejected under 35 U.S.C. § 102 and, in the alternative,                           
               under 35 U.S.C. § 103 over Nishi alone.                                                                             
                       The subject matter of independent claim 1 on appeal appears to be met by the                                
               teachings at columns 1 and 2 under 35 U.S.C. § 102 and clearly would have been obvious                              
               over Nishi’s admitted prior art with respect to Figures 1 and 2.  The claimed processor                             
               side memory for storing image data to be processed comprises the data memory 103 in                                 
               prior art Figure 1 where the processor means recited is met by the CPU 102 which does in                            
               fact process the image data supplied from that memory for placement into the VRAM 104                               
               through the video data processor VDP 101 before the display means claimed presents the                              
               information on CRT 105.  According to the teachings of Nishi regarding Figure 1, the CPU                            
               102 and/or the VDP 101 may control the processing and storing of image data transmitted                             
               from the processor CPU 102.  The VDP 101 comprises the claimed control means since it                               

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