Appeal No. 96-2237
Application 08/113,509
OPINION
We sustain the outstanding rejection of claim 20
only and reverse the rejection of claims 14 through 19 and 21
through 26.
Johnson operates his RISC processor system utilizing
a shared address bus in a manner to accommodate both pipelined
and burst modes of operation where, in the burst mode, simul-
taneous
or concurrent transfers of data and instructions over inde-
pendent data and instruction busses occurs. In pipelined
instruction and data accesses, the pipelined or second in-
struction access cannot complete until the first access has
been completed. Addition- ally, only instruction accesses may
be pipelined or only data accesses may be pipelined but not
either in a sequential order. Note column 6, lines 8
through 14, and column 7, lines 9 through 14. Therefore, the
pipelined teachings of Johnson may not be used by the examiner
to reject independent claims 14 and 21 on appeal which require
that the first and second access cycles be either a data
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