Appeal No. 96-2237
Application 08/113,509
placing the respective memory contents on either of the re-
spective instruction or data busses. There is no requirement
in claim 20, as in independent claims 14
and 21, that the processor complete the second access before
the first access is complete. Appellant's just quoted view at
the bottom on pages 11 and 17 of the principal brief on appeal
apparently confirms our assessment on the operation of John-
son.
We do not agree with appellant's view expressed at
page 14 as to claim 20 that Johnson teaches asserting the
address of the first access on the address bus until the
address memory contents appear on the corresponding instruc-
tion or data bus in a manner contrary to the recitations in
claim 20. There is no such recitation in claim 20. Appel-
lant's views go on to indicate that only after the address
memory contents appear on the bus does the burst-mode protocol
cease to assert the address of the first access and allow the
assertion of the address for a second access, by making refer-
ence to Figure 6. Column 12, lines 45 through 47, of Johnson
8
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