Appeal No. 96-3372
Application No. 07/823,153
after final rejection was filed on August 23, 1995 and was
entered by the examiner.
The disclosed invention pertains to a synchronous and
continuous data decoding circuit for use in a mobile phone.
Data is sent to the mobile phone in a frame of data which
includes at least five repeated data blocks. A 3/5 voting
logic circuit produces bit-wise voting results during the time
that the fifth repeated data block is received. A decoding
circuit receives the bit-wise voting results on a bit-by-bit
basis and creates correction information during the first
repeated data block of the next frame of data. In this manner
corrected data is available in near real time after the
reception of the final repeated block of data.
Representative claim 8 is reproduced as follows:
8. A synchronous and continuous data decoding circuit
in a mobile phone for performing three-out-of-five (3/5)
voting on each of a plurality of data frames, each of said
plurality of data frames comprising at least five repeated
data blocks, the data decoding circuit comprising:
a 3/5 voting logic circuit which receives a first
frame of repeated data blocks when a bit enable signal is
enabled, the 3/5 voting logic circuit including means for
performing 3/5 voting on the at least five repeated data
blocks in the first frame to produce a bit-wise voting result
during the fifth data block of said at least five repeated
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