Appeal No. 1996-3391 Page 6
Application No. 08/160,573
said arithmetic logic unit generating at an output a
multibit digital signal representing a mixed arithmetic
and Boolean combination of said first, second and third
inputs corresponding to said function signal, said mixed
arithmetic and Boolean combination including at least one
combination performing a Boolean function prior to an
arithmetic function.
While Ing-Simmons may not disclose this feature, in our
view, Chu clearly does. Even appellants admit, at page 4 of
the principal brief, that Figure 12 of Chu “clearly shows that
ALU 130 consists of arithmetic logic unit block 496 and 2:1
multiplexer 494" and that Chu “clearly forms the three input
combination with an arithmetic/logical combination of the R and
S inputs formed first in arithmetic logic unit operation block
496 and the Boolean/mask combination formed in 2:1 multiplexer
494 according to the M input.” Thus, there is no question that
Chu discloses an ALU and a multibit digital signal representing
a mixed arithmetic and Boolean combination of the first, second
and third inputs corresponding to a function signal. The only
issue seems to revolve around whether Chu suggests that the
mixed arithmetic and Boolean combination includes “at least one
combination performing a Boolean function prior to an
arithmetic function.”
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