Appeal No. 1996-0455
Application No. 07/511,778
instruction is an instruction using said sub-
instruction
as a result of decoding of said primary instruction, said
sub-instruction held by said sub-instruction holding
means is decoded and executed.
The reference relied on by the examiner is:
Katsura et al. (Katsura) 5,046,023
Sept. 3, 1991
Claims 1 through 3, 5 through 7, 10 and 11 stand rejected
under 35 U.S.C. § 103 as being unpatentable over Katsura.
Reference is made to the briefs and the answer for the
respective positions of the appellants and the examiner.
OPINION
The obviousness rejection of claims 1 through 3, 5
through 7, 10 and 11 is reversed.
With the exception of claim 11, all of the claims on
appeal require the simultaneous access of a first memory
(e.g., main memory) and a second memory (e.g., frame memory)
via two separate ports in the graphics processor. Claim 11 is
specifically directed to the decoding of a primary
instruction, and to the decoding of a sub-instruction that is
used by the primary instruction.
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