Appeal No. 1996-0455
Application No. 07/511,778
The examiner is of the opinion (Answer, page 3) that
Katsura teaches “simultaneous access at column 4, lines 23-
31.”
Appellants argue (Reply Brief, page 5) inter alia that:
Further, the above-noted passage of
Katsura teaches that an address sent to
the second bus is transferred by the bus
connection control means (bus switch 20)
and the first address bus to the system
memory at the same time the first data bus
is connected to the second data bus [Figure 1].
Thus it is quite clear that this passage merely
teaches the simultaneous occurrence of
the transferring of an address from the
second bus to the first bus and the connecting
of the first data bus to the second data
bus so that access can be made to the system
memory 12. This passage of Katsura is not
concerned with the simultaneous access of
system and frame memories via two separate
ports as in Appellants’ invention.
In short, we agree with appellants’ argument that Katsura
neither teaches nor would have suggested to one of ordinary
skill in the art the simultaneous access of the two memories
via two ports of the graphics processor. As a result thereof,
the obviousness rejection of claims 1 through 3, 5 through 7
and
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