Appeal No. 1997-2984 Page 2
Application No. 08/259,967
signals; an "SCL" line for the transmission of a clock signal; a
"Vss" line assigned to a ground potential; and a "Vcc" line for
the transmission of a positive supply potential.
The appellants’ invention is aimed at reducing the number of
lines of an I2C standard bus while preserving compatibility with
its communications protocol. The standard bus is translated to a
modified bus with an added line, which is complementary to a
clock signal of the system. The two power supply lines of the
standard bus are eliminated from the modified bus. The supply
potentials of these lines are instead regenerated from the clock
signal and its complement using a full-wave rectifier.
Claim 26, which is representative for present purposes,
follows:
26. A method for reducing the number of lines in a
bus system comprising the steps of:
receiving, on a bus input, at least one data
signal, a first clock signal, a first system potential,
and a second system potential;
producing a second clock signal which is
complementary to said first clock signal;
transmitting said data signals and said first and
second clock signals over a bus;
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