Ex Parte BAHOUT et al - Page 5



            Appeal No. 1997-2984                                                     Page 5              
            Application No. 08/259,967                                                                   

            Inc. v. Union Oil Co., 814 F.2d 628, 631, 2 USPQ2d 1051, 1053                                
            (Fed. Cir. 1987).  ‘[A]bsence from the reference of any claimed                              
            element negates anticipation.’”  Rowe v. Dror, 112 F.3d 473, 478,                            
            42 USPQ2d 1550, 1553 (Fed. Cir. 1997)(quoting Kloster Speedsteel                             
            AB v. Crucible, Inc., 793 F.2d 1565, 1571, 230 USPQ 81, 84 (Fed.                             
            Cir. 1986)).                                                                                 

                  Here, Wilson describes “[a] power supply circuit for                                   
            converting a digital signal to a [direct current] DC voltage                                 
            ....”  Col. 1, ll. 65-66.  Although “[a] pair of input lines 20                              
            and 21 [of the reference’s power supply circuit] are coupled to                              
            receive digital input signals labeled Tx(+) and Tx(-),” col. 2,                              
            ll. 8-10, neither of the input signals is a clock signal.  To the                            
            contrary, both are data signals.  Specifically, “[t]he                                       
            differential signal lines ... carry digital data ....”  Abs.,                                
            ll. 2-4.                                                                                     

                  Because neither of the signals inputted to Wilson’s power                              
            supply circuit is a clock signal, we are not persuaded that the                              
            applied prior art discloses the limitations of "receiving, on a                              
            bus input, at least one data signal, a first clock signal, a                                 
            first system potential, and a second system potential; producing                             





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